Gaps and trenches such as those found in shallow isolation (STI) structures are commonly employed to electrically isolate elements on semiconductor devices. An STI structure may include a trench or gap formed in an isolation region of a semiconductor substrate that is filled with a dielectric material to hinder the electrical coupling of nearby device structures (e.g., transistors, diodes, etc.). As the device density on integrated circuits continues to increase, the size and distance between device structures continue to decrease. However, the vertical heights of the STI trenches normally do not decrease as fast as their horizontal widths, resulting in gaps and trenches with larger ratios of height to width (e.g., higher aspect ratios).
While the ability to make device structures with increasing aspect ratios allows more of the structures (e.g., transistors, capacitors, diodes, etc.) to be packed onto the same surface area of a semiconductor chip substrate, it has also created fabrication problems. One of these problems is the difficulty of completely filling the gaps and trenches in these structures without creating a random void or seam during the filling process. Filling gaps and trenches with dielectric materials like silicon oxide is necessary to electrically isolate nearby device structures from each other to minimize electrical noise and current leakage. As aspect ratios increase, it becomes more difficult to fill deep narrow trenches without creating a void or seam in the dielectric material that fills the trench.
However, from an STI deposition process and isolation performance point of view, voids formed near the bottom of the trench may be acceptable and can have the benefit of good isolation since air has a dielectric constant, k value of only 1. However, current processes in forming voids near the bottom of the trenches may be problematic. The sizes, shapes, locations, and densities of the voids formed may not all be consistent. This could result in unpredictable and inconsistent post-deposition processing of the dielectric layer, such as non-uniform etching, polishing, annealing, etc. The voids formed in the finished devices may also create variations in the dielectric qualities of the gaps and trenches in device structures. This can result in erratic and inferior device performance due to electrical crosstalk, charge leakage, and in some instances, shorting within the device, among other problems.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for an improved process of forming bottom voids in trenches and gaps that avoids the problems associated with conventional processes.